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Need help with this problem writing the Verilog module for washing machine contr

ID: 2990388 • Letter: N

Question

Need help with this problem writing the Verilog module for washing machine controller.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:49:40 10/20/2014
// Design Name:
// Module Name: DMC
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DMC(
input clock,
input reset,
input start,
input [7:0] humidity_sensor,
input [7:0] temperature_sensor,
output reg high_heater,
output reg low_heater,
output reg motor_cw,
output reg motor_enable
);
   reg [1:0] state, nextstate
        
   //DFF
   always @ (posedge clock)
   begin
   if (reset)state<=IDLE;
   else state<=nextstate;
   end
     
   always @ (state)
   begin
   high_heater=0;
   low_heater=0;
   motor_cw=0;
   motor_enable=0;
   end
     
   case(state)
   IDLE:
   if(start)
   nextstate=PREHEAT;
   else nextstate=IDLE;
   PREHEAT:
   if(IDLE)
   nextstate=TUMBLE;
   else nextstate=PREHEAT;
   TUMBLE:
   if(PREHEAT)
   nextstate=IDLE;
   else nextstate=TUMBLE;
   default: deault => 0;
   end
     
   case(TUMBLE)
   case1: if (TUMBLE<=5)
   motor_cw = high_heater;
   end

   case2: if (TUMBLE<=0)
   motor_enable = low_heater;
   end
     
   case3: if (temperature_sensor<=180)
   high_heater = 0 && low_heater = 0;
   end
     
   case4: if (temperature_sensor<=160-180)
   high_heater = 0;
   end
     
   case5: if (temperature_sensor>=160)
   high_heater = 1;
   end
     
   case6: if (humidity_sensor >= 5)
   nextstate = IDLE;
   end
     
     
   endcase
   end
     
     
     

endmodule

Draw a state diagram and write a Virile module for a washing machine controller using Finite Sale Machine Io perform the following tasks: The machine is in idle state. When the Start button is pressed, the FSM starts to let water to flow into the washing machine by turning on the inlet valve. When the water level full sensor input indicates a high, the inlet valve is closed. The machine will turn the motor clockwise for live seconds, by setting the Motor CW high. Then, it turns the motor counter clock wise for five seconds by setting Motor CW low. Perform this for 10 minutes. The machine drains water by turning on the outlet valve. This continues until the water level empty sensor indicates a high. The machine will enter the "SPIN" state by setting Motor _CW high for 10 minutes. The machine returns to the Idle state. This is module has two inputs: a I-H/ clock, and an active-high reset, and three outputs: inlet valve, outlet _valve. and motor _CW. It also accepts Start input, and water level high and water level low.

Explanation / Answer

module wmc (input clk,
             input reset,
             input start,
             input full_sensor,
             input empty_sensor,
             output reg inlet_valve,
             output reg outlet_valve,
             output reg motor_cw,
             output reg motor_en);
reg [3:0]counter;
reg [2:0]state;
parameter idle=3'b000,strt=3'b001,motor=3'b010,drain=3'b011,spin=3'b100;

always @ (posedge clk)
begin
if (reset)
state = idle;
else
begin
case (state)
idle:
begin counter=0;
       if(start)
      state = strt;
       else state = idle;
       end

strt:
if(full_sensor)
begin
inlet_valve = 0;
state = motor;
end
else inlet_valve = 1;
      
   motor:
   begin
     motor_en = 1;
     counter = counter+1;
     if(counter <=6 )
       motor_cw = 1;
     else if (counter <= 11)
       motor_cw = 0;
     else
       begin
       state = drain;
       counter = 0;
       motor_en= 0;
       end
end

drain:
if(empty_sensor)
    begin
    outlet_valve = 0;
    state = spin;
    end
else outlet_valve = 1;
  
    spin:
    begin
    counter = counter+1;
    if(counter <= 11)
      motor_cw = 1;
    else
      begin
      motor_cw = 0;
      state = idle;
    end
end
endcase
end
end
endmodule