Constder a c PU tint are priority interupt in which higher priority interupts ar

Question

Constder a c PU tint are priority interupt in which higher priority interupts ar lowed/andled whie Question 3: [4 Consider a CPU that uses parallel hardware priority interrupt in which higher priority interrupts are allowed/handled while a lower priority interrupts are being handled. The following is a list of steps that will be performed by the CPU as a result f receiving an interrupt. These steps are not listed in the right order or execution. Reorder these steps by indicating the tep numbers (I to 8) in the left column of the table. PC VAD Restore the CPU registers Set the mask bits corresponding to lower priority interrupts Execute instructions to perform the I/O operations needed to handle the interrupt Save the return address on the stack Save the CPU registers Clear the mask bits corresponding to lower priority interrupts Pop an address from stack and set PC to the popped address

Explanation / Answer

Below are the reordered sequence of steps performed by CPU while handling High priority interrupts:

Related Questions

Navigate

• Browse (All)
• Browse C
• Subjects

---