Please answer the 4 multiple choice questions below: An Intel x-86 CPU running i
ID: 3675331 • Letter: P
Question
Please answer the 4 multiple choice questions below:
An Intel x-86 CPU running in virtual memory mode is always translating virtual addresses to a physical addresses. In all cases, the translation requires the CR-3 register and a table walk. True False The content of a valid PTE (Page Table Entry), that points to a physical DRAM page of user data or code is always cached in the CPU's TLB (Translation Look aside Buffer) when it is first located during a table walk. True False On a single CPU system, when a thread with a priority that is higher than the current running thread is moved into the ready state, we expect it to move to the run state quickly, displacing the current running thread. What type of transition does the displaced running thread follow in this situation ? the running thread is sent to the block state the running thread shares the run state with the higher priority thread the running thread is forced out via the exit path the running thread is preempted When translating a virtual to physical address using a table walk, some of the most significant bits of the virtual address are used to access PTEs (Page Table Entries). If we have a 24 bit virtual address used in a system that has 2KB pages (211 = 2048 byte pages), how many virtual pages (i.e. how many total PTEs) are there in the total virtual address space ? 32 K 4 K 64 K 16K 8KExplanation / Answer
1. True , To get the base address of the page directory table, simply read the contents of the CR3 register, which acts as the page directory base registers (PDBR) and points to the physical address of the first table.
2. True , When a virtual memory address is referenced by a program, the search starts in the CPU. First, instruction caches are checked. If the required memory is not in these very fast caches, the system has to look up the memory’s physical address. At this point, TLB is checked for a quick reference to the location in physical memory.
3. (Option 1) In the single-core (simple) case, The running thread blocks and the highest-priority ready thread that's at the head of its priority's queue is chosen and allowed to run.
4. 8K