Memory Addressing and Decoding 1) A computer system is specified as having a 32-
ID: 3682690 • Letter: M
Question
Memory Addressing and Decoding 1) A computer system is specified as having a 32-bit data bus and a 32-bit address bus: a) What is the maximum number of addressable locations in this system? b) How many 256M x 8 memory devices are required to fill this address space? c) Construct a memory map showing the start and end address of each 32-bit block. d) How many address lines go to each device, and how many need to be decoded? e) Design the required address decoding for the device chip selects. (Show block diagram and/or Verilog code.) f) Show how the memory devices will be arranged on the address, data, and control buses. Use a suitable drawing program such as Visio or PowerPoint.Explanation / Answer
I am answering only first 4 parts acc. to chegg guideline
a) 232 address locations
b) 256M * 8 = 28 * 210+10 *23 = 231 hence 232/231 i.e. 2 devices are required
c)
1st memory block start: 000...000000 (32 bits)
end: 01111111...1111(32 bits)
2nd memory block start: 10000...00000(32 bits)
end: 1111...1111111(32 bits)
d) 31 address lines go into each device and only 1 line needs to be decoded.