Assignment 2 Notes: Submission MUST be only 1 PDF or Doc format document of type
ID: 3728800 • Letter: A
Question
Assignment 2 Notes: Submission MUST be only 1 PDF or Doc format document of typed report. (For example, hand written scanned file is not acceptable.) Do not upload a zip file containing multiple files Only 1 file can be uploaded (any new upload will replace the old upload). The deadline is timed, and will stop accepting new upload at 11:59pm on the designated date. In the report, clearly mention the type of HDL code (ie. Verilog, VHDL, or System Verilog) that you have used for solution of these problems. Use only one for your entire report To simulate and synthesize your code, you need to install Quartus II (Web Edition) in your computer from Altera Website: http:lldl.altera.com/?edition web. Alternately, you can access this simulation software at a computer in ET227 (aka Microprocessor Lab). · . 1. a) Write a HDL code (either Verilog, SystemVeirlog, or VHDL) of the ALU as shown below, where N = 32, The two inputs are labeled as A and B, while the output is labeled as Y. The 3-bit select inputs are labelled as F. The desired functionality of the ALU is given in the following table. Function A AND B A OR B A +B (Unused) A AND-B A OR B A-B SLT(Set Less Than) F [2:0 001 100 101 110 b) Write a testbench to functionally verify your code developed in part a. Provide simulation results using this testbench of input/output waveforms that functionally verifies the ALU operation as outlined in the table (at least 1 example for each function). Hint: To understand the function: SLT (set less than), refer to the textbook, sec. 5.2.4, pp. 248-250Explanation / Answer
Verilog Code
module ALU(y,a,b,f);
input [31:0]a,;
input [31:0]b;
input [2:0]f;
output [31:0]y;
always @(f) // whenever there is a change in 'f' this block gets executed
begin
case(f) // switch case starts
0: y<= a & b;
1: y<= a | b;
2: y<= a + b;
4: y<= a & (~b);
5: y<= a | (~b);
6: y<= a - b;
7: begin
if (a[31] != b[31]) begin
if (a[31] > b[31]) begin
y <= 1;
end else begin
y <= 0;
end
end else begin
if (a < b)
begin
y <= 1;
end
else
begin
y <= 0;
end
end
end
endcase
end
Testbench
module ALU_tb;
reg [31:0] a;
reg [31:0] b;
reg [2:0]f;
wire [31:0]y;
ALU DUT1(y,a,b,f); // calling the design
initial begin
a=32'b10101000011111100000111010110010; // assigning a
b=32'b10110110000101011110001011110001; // assigning b
for(int i=0;i<8;i=i+1)
begin
{f}=i;
#10;
end
$display("when f = %b y = %b",f,y);
end
endmodule