This diagram is the simple 1 cycle-per-instruction 32-bit MIPS architecture we d
ID: 3739026 • Letter: T
Question
This diagram is the simple 1 cycle-per-instruction 32-bit MIPS architecture we discussed in class. 0 MI Add ALU Add result 4 Shift left 2 RegDst Branch MemRead MemtoRe Instruction[31-2? Control ALU MemWrite ALUSrc RegWrite Instruction [25-21] Read register 1 Read Read PCaddress Instruction [20-16 Read data 1 Zero ALU ALU result register 2 Read Address data Instruction uWrite Read 1Write [31-0) InstructionInstruction [15egister data2 memory data Registers Data Write data memo Instruction [15-0] 16 Sign- 32 ALU control extend Instruction [5-0 For the following questions, assume that PC-0x12343210, where the encoding for the MIPS instruction sw $7, 20($6) is stored As a review, the MIPS sw $ra, D($rd) instruction stores the contents of register ra to memory location D($rd); like x86-64, the value of D($rd) is determined by adding the displacement value D to the contents of register rdExplanation / Answer
Option 2
0x12343214
as PC = 0x12343210 then program jumps to instruction SW $7,D($6) which menas the content of register $7 is store at the 4 + address of register $6. Once the SW instruction executed program return back to the address hold by the PC and execute its next instruction. As the instruction size in MIPS architecture is 4 byte(32 bit) therefore the address of next instruction is Address of PC+ 4 = 0x12343210 + 4 = 0x12343214.