Consider three processors with different cache configurations: Cache 1: Direct m
ID: 3779110 • Letter: C
Question
Consider three processors with different cache configurations: Cache 1: Direct mapped with one-word blocks Cache 2: Direct mapped with four-word blocks Cache 3. Two-way set associative with four-word blocks The following miss rate measurements have been made: Cache 1: Instruction miss rate is 4%; data miss rate is 6%. Cache 2: Instruction miss rate is 2%; data miss rate is 4%. Cache 3: Instruction miss rate is 2%; data miss rate is 3%. For these processors, one-half of the instructions contain a data reference. Assume that the cache miss penalty is 6 + Block size in words. The CPI for this workload was measured on a processor with cache 1 and was found to be 2.0. Determine which processor spends the most cycles on cache misses.Explanation / Answer
We know that
The miss penalty can be calculated as,
Miss Penalty=6 + word block size
Given that one-half the instructions conatains data reference which = 50%
Calculation for Processor 1:
Miss penalty = 6 + 1 = 7 cycles
Stall cycles/instruction = 4% × 7 + 50% × 6% × 7 = 0.28 + 0.21 = 0.49
Calculation for Processors 2:
Miss penalty = 6 + 4 = 10 cycles
Stall cycles/instruction = 2% × 10 + 50% × 4% × 10 = 0.2 + 0.2 = 0.4
Calculation for Processor 3:
Miss penalty = 6 + 4 = 10 cycles
Stall cycles/instruction = 2% × 10 + 50% × 3% × 10 = 0.2 + 0.15 = 0.35
So,the processor 1 has maximum Stall cycles/instruction and hence Processor 1 spends the most cycles on cache misses.