Please help with the VHDL code for the timing (25 secs and 4 secs). Below are th
ID: 3821345 • Letter: P
Question
Please help with the VHDL code for the timing (25 secs and 4 secs). Below are the constraints.
As part of the project requirement, following timing constraint must be satisfied: Side Side Side Main Main Main Main Side Fourth state: 4 seconds First state: 25 seconds Second state: 4 seconds Third state: 25 seconds minimum or as long as maximum or until there is no vehicle on there is no vehicle on side street side street The above timing requirements can be viewed as a high level state machine where the variables are: Vs Presence of vehicle on side street TL Visibility of Long timer (25 sec) TS Visibility of Short timer (4 sec) Both timer(s) need to be appropriately triggered for successful operation of the TSC.Explanation / Answer
library ieee;
se ieee.std_logic_1164.all;
entity traffic_signalling is
port (
clk, reset : in bit;
r, y, g : out bit);
end traffic_signalling;
architecture behavior of traffic_signalling is
TYPE state IS (R, Y, G);
CONSTANT TL : INTEGER := 1500;
CONSTANT TS :INTEGER := 240;
SIGNAL present_state, next_state : state;
SIGNAL time: INTEGER RANGE 0 TO TL;
BEGIN
PROCESS(clk, reset)
VARIABLE count : INTEGER RANGE 0 TO TL;
BEGIN
IF (reset = '1') THEN present_state <= R;
ELSIF (clk'event) AND (clk = '1') THEN count := count +1;
IF (count = time) THEN present_state <= next_state;count := 0;
END IF;
END IF;
END PROCESS;
PROCESS (present_state)
BEGIN
CASE present_state IS
WHEN R => r<=’1’; y <=‘0’; g <=‘0’;
time <= TL;
next_state <= Y;
WHEN Y => r <=‘0’; y <=‘1’; g <=‘0’;
time <= TS;
next_state <= G;
WHEN G => r <=‘0’; y <=‘0’; g <=‘1’;
time <= TL;
next_state <= Y;
WHEN Y => r <=‘0’; y <=‘1’; g <=‘0’;
time <= TS;
next_state <= R;
END CASE;
END PROCESS;
END behavior;