Answer the following questions about cache coherency protocols in a mulit-proces
ID: 3824210 • Letter: A
Question
Answer the following questions about cache coherency protocols in a mulit-processor system.
a) What is the main advantage of the MESI snoopy cache coherency protocol used in a system in which each processor has a separate cache compared to a snoopy cache coherency protocol that uses only 3 states M, S and I (modified, shared and invalid)?
b) Should the current MESI state be changed from M in response to a write hit from a remote processor to an already modified line in a local cache? Explain your answer.
c) If the 3-state MSI cache coherency protocol is used with a direct mapped cache containing 1048576 lines each of which is 512 bytes in size, what is the total number of bits required to implement the cache coherency protocol for a single cache?
Explanation / Answer
Hi,
Please find the answer to the questions below:-
a)
The MESI refers to Modified(M), Exclusive(E), Shared(S), Invalid(I) .It has a major advantage over MSI protocol by considering the following example:-
Lets a block A has to be read which no other processor has.
Now in MSI case
There will be two bus transactions that will take place:-
a) Request to read the block
b) Request to read a block to processor which also doesn’t have it already.
MESI protocol overcomes this limitation by adding an Exclusive state, which results in saving a bus request. The reason because when one enters in EXCLUSIVE, all accesses to that processor will be exclusive and in exclusive read mode Read to the block is a Cache Hit. No bus transactions are generated.
b)
No, the current MESI state must not be changed from M in response to a write hit from a remote processor to an already modified line in a local cache as in MESI A write can only be performed if the cache line is in the Modified or Exclusive state.
In this case:-
i) State remains the same.
ii) Write to the block is a Cache hit.
c)
Total number of lines=1048576
Size of line=512
To implement 1048576 lines the bits required will be 2^20=1048576
20 bits are required to implement the cache coherency protocol for a single cache.
Please let me know in case any clarification is required.