For these next questions, please show all of your work. Assume that main memory
ID: 3829675 • Letter: F
Question
For these next questions, please show all of your work.
Assume that main memory access requires 70ns, and that memory accesses are 36% of all instructions. The following table shows data for L1 caches attached to each of two processors, P1 and P2:
L1 Size
L1 Miss Rate
L1 Hit Time
P1
2 KiB
8.0%
0.66ns
P2
4 KiB
6.0%
0.90ns
Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates?
What is the average memory access time for P1 and P2?
Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster?
L1 Size
L1 Miss Rate
L1 Hit Time
P1
2 KiB
8.0%
0.66ns
P2
4 KiB
6.0%
0.90ns
Explanation / Answer
1.) Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates?
P1 clock = 1/0.66 = 1.6GHz
P2 clock = 1/0.90 = 1.9GHz
2.) What is the average memory access time for P1 and P2?
AMAT = hit time + miss rate * miss penalty
P1 AMAT = 0.66 + 0.08 * 70 = 6.26ns
P2 Amat = 0.90 + 0.06 *70 = 5.1ns
3.)Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster?
CPI = base CPI + instruction miss CPI + data miss CPI
P1 CPI = 1.0 + 0.08 * (70/.66) + .36 *0.08*(70/.66)
= 12.5 CPI
P2 CPI = 1.0 + 0.06 * (70/.90) + .36 *0.06*(70/.90)
= 7.34 CPI
This implies timer 2 is faster.