CSCI 3211 Computer Architecture I Homework #5 1. Assume the structure of a Tag C
ID: 3873845 • Letter: C
Question
CSCI 3211 Computer Architecture I Homework #5 1. Assume the structure of a Tag Cache and Main Memory as the following; 2 010010010 0001101010 010101010 1111001010 2 2 0 1101001001 00110010101 If the Direct Mapped Cache method is implemented, what is the structuer of Cache RAM? Assume the main memory is organized as the following, in which the represented data are stored in Chace RAM 2. 0 111101010 01010101 0001110101 111010101 1100011001 111011101 What is the structure of Tag Cache with regard to Sector Mapped Cache such that there are S cache sectors.Explanation / Answer
Sol,
1) Here Block size = 8
lines = 32/8 = 4
As we know mapping can done in three ways :
RAM has different memory locations. we know , memory locations are grouped into blocks of 2n locations where n represents the number of bits which are used to identify a word within a block. These n bits are found at the least-significant end of the physical address. if n=2 then each block of memory, there are 22 = 4 memory locations.
Direct mapping concludes as below :
If 2S mod 2r = 0, then RAM is divided into 2s ÷2r = R regions as follows:
1. region 0’s blocks nos. : 0,...,2r 1, mapped to 0,...,2r 1 lines of cache,
2. region 1’s blocks nos.: 2r,...,2.2r 1, mapped to 0,...,2r 1 lines of cache,
3. region R 1’s block nos. : R 1×2r ,...,R.2r 1, mapped to 0,...,2r 1 lines of the cache.
if 2s is total no. of blocks in
RAM, and 2r is no. of rows in cache, with row size == block size=2w words, then ith block of RAM is mapped to jth row of cache as follows, so that j = i mod 2
Thus, a row address corresponding to r bits from address eld is a direct index to the block position in a region.