CSCI 3211 Computer Architecture I Homework #5 1. Assume the structure of a Tag C

Question

CSCI 3211 Computer Architecture I Homework #5 1. Assume the structure of a Tag Cache and Main Memory as the following; 2 010010010 0001101010 010101010 1111001010 0 110100101 1101001001 0 If the Direct Mapped Cache method is implemented, what is the structuer of Cache RAM? 2. Assume the main memory is organized as the following, in which the represented data are stored in Chace RAM. 111101010 01010101 0001110101 111010101 1100011001 111011101 What is the structure of Tag Cache with regard to Sector Mapped Cache such that there aure 5 cache sectors

Explanation / Answer

1. Hint :

Fundamentally, each of the main memory address can be divided into [block number/Tag bits | cache line/bits | block offset bits] in order to map them into the cache memory. As the cache memory is much smaller than the main memory, hence the addresses of main memory are stored in round robbin manner inside the cache. If any address is found inside cache, then we say cache hit and if not found, we say cache miss. In direct mapped cache, each block can go into one line.

There are max 1 bits as per main memory addressing and tag bit is 2 (which may become 01, 10, 00 and 11) followed by cache lines and then block offset.

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