On an ARMv7-M processor, assuming that [R1] = 0x7F0E0C2D, [R2] = 0x2468ACE0, [R3
ID: 3883136 • Letter: O
Question
On an ARMv7-M processor, assuming that [R1] = 0x7F0E0C2D, [R2] = 0x2468ACE0, [R3] = 0x1048B3C5, [N-bit] = 0, [Z-bit] = 0, [C-bit] = 1, [V-bit] = 0, predict the 32-bit [R1] and all four condition flags in APSR after an ARM arithmetic/logical instruction is executed in EACH case. (These instructions are NOT executed one after the other one; instead, each instruction starts with the initial conditions given in the statement.)
(a) ADCS R1, R3, ROR #0x18
(b) ADDW R1, R2, #0xF1B
(c) SUBS R1, R2, R3
(d) RSBS R1, R2, #0x12
(e) SBCS R1, R3, LSL #12
(f) EORS R1, R2, R3, LSR #4
(g) BICS R1, R2, R3, RRX
(h) ANDS R1, R2, ASR #28
(i) ORR R1, R2, R3
(j) ORN R1, R2, #0xB600B600
Explanation / Answer
R1= 0x7F0E0C2D = 0111 1111 0000 1110 0000 1100 0010 1101
R2= 0x2468ACE0 = 0010 0100 0110 1000 1010 1100 1110 0000
R3= 0x1048B3C5 = 0001 0000 0100 1000 1011 0011 1100 0101
[N-bit] = 0, [Z-bit] = 0, [C-bit] = 1, [V-bit] = 0,
1. ADCS R1,R3, ROR #0x18
R3, ROR #0x18
R3= 0100 1000 1011 0011 1100 0101 0001 0000 = 0x48B3C510
Result: C7C1D13E
After ADCS R1,R3, ROR #0x18
N = 0;
Z = 0;
C = 0;
V = 0;
2. ADDW R1, R2, #0xF1B
Result= 0xA376C828
N = 0;
Z = 0;
C = 0;
V = 0;
3. SUBS R1, R2, R3
Result= 141FF91B
N = 0;
Z = 0;
C = 0;
V = 0;
4. RSBS R1, R2, #0x12
Result: -2468ACCE
N = 1;
Z = 0;
C = 1;
V = 0;