On an ARMv7-M processor, assuming that [R1] = 0x7F0E0C2D, [R2] = 0x2468ACE0, [R3
ID: 3883407 • Letter: O
Question
On an ARMv7-M processor, assuming that [R1] = 0x7F0E0C2D, [R2] = 0x2468ACE0, [R3] = 0x1048B3C5, [N-bit] = 0, [Z-bit] = 0, [C-bit] = 1, [V-bit] = 0, predict the 32-bit [R1] and all four condition flags in APSR after an ARM arithmetic/logical instruction is executed in EACH case. (These instructions are NOT executed one after the other one; instead, each instruction starts with the initial conditions given in the statement.)
(e) SBCS R1, R3, LSL #12
(f) EORS R1, R2, R3, LSR #4
(g) BICS R1, R2, R3, RRX
(h) ANDS R1, R2, ASR #28
(i) ORR R1, R2, R3
(j) ORN R1, R2, #0xB600B600
Explanation / Answer
R1= 0x7F0E0C2D = 0111 1111 0000 1110 0000 1100 0010 1101
R2= 0x2468ACE0 = 0010 0100 0110 1000 1010 1100 1110 0000
R3= 0x1048B3C5 = 0001 0000 0100 1000 1011 0011 1100 0101
[N-bit] = 0, [Z-bit] = 0, [C-bit] = 1, [V-bit] = 0,
(e) SBCS R1, R3, LSL #12
R3,LSL#12 makes
R1 = 0111 1111 0000 1110 0000 1100 0010 1101 = 7F0E0C2D
R3 = 1110 0000 1100 0010 1101 0000 0000 0000 = E0C2D000
Result R1 = -61B4C3D4
Flag status
N = 1; Since the result is negative
Z = 0; Since the result is not zero
C = 0; Since it is used by the sbcs instruction
V = 0; Since the overflow won't occur with this instruction
(f) EORS R1, R2, R3, LSR #4
After R3, LSR #4
R3 = 0000 0001 0000 0100 1000 1011 0011 1100
R2 = 0010 0100 0110 1000 1010 1100 1110 0000
Result R1= 256C27DC = 0010 0101 0110 1100 0010 0111 1101 1100
N = 0; Since the result is non negative
Z = 0; Since the result is not zero
C = 1; Since it is set previously
V = 0; Since the overflow doesn't occur with this instruction
(g) BICS R1, R2, R3, RRX
After R3,RRX
R3 = 1000 0000 1000 0010 0100 0101 1001 1110
R2 = 0010 0100 0110 1000 1010 1100 1110 0000
Result =480= 0000 0000 0000 0000 0000 0100 1000 0000
N = 0; Since the result is non negative
Z = 0; Since the result is not zero
C = 1; Since it is set by the RRX instruction
V = 0; Since the overflow doesn't get effected with this instruction
(h) ANDS R1, R2, ASR #28
After R2, ASR #28
R2 = 0000 0000 0000 0000 0000 0000 0000 0010
R1 = 0111 1111 0000 1110 0000 1100 0010 1101
Result = 0000 0000 0000 0000 0000 0000 0000 0000
N = 0; Since the result is non negative
Z = 1; Since the result is zero
C = 1; Since it is not reset by the instruction
V = 0; Since the overflow doesn't get effected with this instruction
(i) ORR R1, R2, R3
R2= 0x2468ACE0 = 0010 0100 0110 1000 1010 1100 1110 0000
R3= 0x1048B3C5 = 0001 0000 0100 1000 1011 0011 1100 0101
Result = R1=3468BFE5 = 0011 0100 0110 1000 1011 1111 1110 0101
N = 0; Since this instruction doesn't effect the flags
Z = 0; Since this instruction doesn't effect the flags
C = 1; Since this instruction doesn't effect the flags
V = 0; Since this instruction doesn't effect the flags
(j) ORN R1, R2, #0xB600B600
This instruction performs OR operation of R2 with the inverted bits of 0xB600B600
R2 = 0010 0100 0110 1000 1010 1100 1110 0000
Or 0100 1001 1111 1111 0100 1001 1111 1111
Result R1 = 0110 1101 1111 1111 1110 1101 1111 1111 = 0x6DFFEDFF