Please give short answers for the questions below. Thank you! Table 6-1: Sum and
ID: 3885968 • Letter: P
Question
Please give short answers for the questions below. Thank you!
Table 6-1: Sum and Carry Outputs for Full Adder
Cin
A
B
Cout
Cin
A
B
Cout
0
0
0
1
1
1
0
0
0
1
0
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
1
0
1
1
1
0
0
Table 6-2: Observed Outputs for Full Adder Implementation 1
Cin
A
B
Cout
Cin
A
B
Cout
0
0
0
1
1
0
1
0
0
1
0
0
1
0
1
1
1
0
1
0
0
1
0
0
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
6.2 Implementation 2
1) Open the Multisim file Digital_Exp_06_Part_01b.
Cin
A
B
Cout
Cin
A
B
Cout
0
0
0
1
1
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
1
1
0
0
0
1
1
1
0
1
1
1
1
0
Questions for Part 1
1) How could you configure a full adder to operate as a half-adder?
2) Do the outputs of the full adders in Table 6-2 and Table 6-3 match the expected values in Table 6-1?
3) What advantage, if any, does the full adder in Digital_Exp_06_Part_01b have over the full adder in
Digital_Exp_06_Part_01a?
Cin
A
B
Cout
Cin
A
B
Cout
0
0
0
1
1
1
0
0
0
1
0
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
1
0
1
1
1
0
0
Explanation / Answer
1) To make the full adder as the half adder, fix the Cin bit to logic Zero(0) permanently..
2) The outputs in table 6-2 matches the output of table 6-1 completely, while output in table 6-3 doesn't match to the output of 6-1 for below reason:
with (1,1,0) the output should be (1,0) as per table 6-1 but it is (0,1) as per table 6-2... Hence incorrect.
3) As i am not able to see the design of both parts, i would not be able to answer it.