Consider the internal structure of the pseudo-CPU discussed in class augmented w
ID: 675098 • Letter: C
Question
Consider the internal structure of the pseudo-CPU discussed in class augmented with a Stack Pointer (SP) and a 16-bit Temporary (TEMP) registers. Suppose the pseudo-CPU can be used to implement the AVR instruction CALL label (Long Call to a Subroutine). CALL label is a four-byte instruction. Give the sequence of micro operations required to Fetch and Execute CALL label. Your solution should result in no more than 12 micro operations for the fetch cycle (i.e., fetch the 16-hit opcode into the IR and the 16-bit address into TEMP) and 7 micro operations for the execute cycle). You may assume the SP register has the capability to increment/decrement itself. Assume the PC is currently pointing to the CALL instruction and MDR register is 8-bit wide, and SP. PC. IR, and MAR are 16-bit wide. Note that since PC is 16 bits, only the lower 16 bits of the target address (i.e.. label) arc used. In other words, the upper 16 bits represent the opcode and the lower 16 bits represent the target address for the subroutine call. Also, assume Internal Data Bus is 16-bit wide and can handle 8-bit or 16-bit transfers in one micro operation. Clearly state any other assumptions made.Explanation / Answer
Solution : Fetch and Execute micro operations are :
R3 R1 + R2 Contents of R1 plus R2 transferred to
R3 R3 R1 – R2 Contents of R1 minus R2 transferred to
R3 R2 R2 Complement the contents of R2 (1’s complement)
R2 R2 + 1 2’s complement the contents of R2 (negate)
R3 R1 + R2 + 1 R1 plus the 2’s complement of R2 (subtraction)
R1 R1 + 1 Increment the contents of R1 by one
R1 R1 – 1 Decrement the contents of R1 by one