The diagram below is an attempt to build a 3-bit majority detector (Y = AB + AC
ID: 1846447 • Letter: T
Question
The diagram below is an attempt to build a 3-bit majority detector (Y = AB + AC + BC). Is the circuit correct? Prove your answer.
8. This circuit is drawn in the Multisim application and shows three inputs, labeled A, B and C going into a circuit that consists of 5 two-input NAND gates, in three stages, with an output labeled
The diagram below is an attempt to build a 3-bit majority detector (Y = AB + AC + BC). Is the circuit correct? Prove your answer. This circuit is drawn in the Multisim application and shows three inputs, labeled A, B and C going into a circuit that consists of 5 two-input NAND gates, in three stages, with an output labeled "Y". Inputs A, B and C are shown on the left of the diagram denoted using white 1/16 inch squares. Output Y is shown on the right of the diagram denoted using a white 1/16 inch square.Explanation / Answer
First let us the output logic of Y from the figure.
Y = ((((AC)' (AB)')') ((BC)'))'
The truth table for this expression is
Hence the circuit diagram shown above is not the 3 bit majority detector.
A B C (AC)'=d (AB)'=e (de)'=f (BC)'=g Y = (fg)' AB+BC+AB 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1