Imagine a state machine that has a two-bit input in[1:0] and an output out. Cons
ID: 2249644 • Letter: I
Question
Imagine a state machine that has a two-bit input in[1:0] and an output out. Consider the initial state to be one where out = 0. In this state machine, all output changes should occur in synch with the clock.
The output should only change in response to the following input sequences. Each two-bit value represents an input condition that – along with a clock trigger – causes a state change. As indicated above, the output should only change on the clock trigger following the second two-bit value in the sequence.
The clocked input sequence ins[1:0] = 10, 00 causes the output to become 0.
The clocked input sequence ins[1:0] = 01, 00 causes the output to become 1.
The clocked input sequence ins[1:0] = 11, 00 causes the output to toggle (complement) its value
Implement the state machine using a dense state assignment and D flip-flops. The module you write should instantiate the proper number of flip-flops to implement a dense state assignment. Use continuous assignments for the D flip-flop input logic and the output logic for Z. Use the following model for your module declaration: module state dense (clock, init, in, out, state); clock, init; input input1:0] in,; output [?:0] state; 1/? is something that should be changed. How many states are there?Explanation / Answer
module state_dense (clock, init, in, out, state);
input clock, init;
input [1:0] in;
output out;
output [1:0] state;
reg out, next_out;
reg [1:0] state, next_state;
parameter S_00 = 2'b00,
S_01 = 2'b01,
S_10 = 2'b10,
S_11 = 2'b11;
always @ (posedge clock) begin // assigning at the posedge of the clock both out and state
if (init) begin
out <= 1'b0;
state <= S_00;
end else begin
out <= next_out;
state <= next_state;
end
end
always @ (*) begin // Next state and Next output evaluation always block
next_out = 1'b0;
case(state)
S_00 : if (in == 2'b00) begin
next_state = S_00;
end else if (in == 2'b10) begin
next_state = S_10;
end else if (in == 2'b10) begin
next_state = S_10;
end else if (in == 2'b11) begin
next_state = S_11;
end
S_01 : if (in == 2'b00) begin
next_state = S_00; next_out = 1'b1;
end else if (in == 2'b10) begin
next_state = S_10;
end else if (in == 2'b10) begin
next_state = S_10;
end else if (in == 2'b11) begin
next_state = S_11;
end
S_10 : if (in == 2'b00) begin
next_state = S_00;
end else if (in == 2'b10) begin
next_state = S_10;
end else if (in == 2'b10) begin
next_state = S_10;
end else if (in == 2'b11) begin
next_state = S_11;
end
S_11 : if (in == 2'b00) begin
next_state = S_00; next_out = ~out;
end else if (in == 2'b10) begin
next_state = S_10;
end else if (in == 2'b10) begin
next_state = S_10;
end else if (in == 2'b11) begin
next_state = S_11;
end
endcase
end
/* The state machine should change the output only when following condition are met
1. in[1:0] 10 -> 00 :: out = 1'b0
2. in[1:0] 01 -> 00 :: out = 1'b1
3. in[1:0] 11 -> 00 :: out = toggle
*/
endmodule