Please with explaination And how i work step by step 7. Experimental work Step 1
ID: 3700527 • Letter: P
Question
Please with explaination And how i work step by step
7. Experimental work Step 1-Full Adder Verilog Code 1. Create a Verilog code that designs the functions of a full adder a. Compile your Verilog HDL source file using Quartus b. Test and verify the operation of your circuit using a test bench. c. Save the waveform output, and submit it to Moodle. d. Create a symbol for your full adder, and save it in your project director Step 2- Adder and Subtractor Circuit 2. Create a block diagram that does the function of adding or subtracting 3 bit numbers. a. Compile your Verilog HDL source file using Quartus, targeting it for Altera Cyclone IVE /V b. Test and verify the operation of your circuit in a waveform file. c. Save the waveform output, and submit it to Moodle. d. Implement your design on the FBGA board. Test and verify the operation of your circuit, and demonstrate it to your lab instructor. i. Connect your inputs (A2, A1, A0) and (B2, Bl, BO) to switches 12 17. Connect your input selector M to switch 0 i. Connect your outputs (S2, S1, and S0) to LEDs G7, G6, and G5. Connect you Carry-out (C3) to LED G4 Below is a summarized connected to on your FBGA board. block diagram of your outputs and inputs and the devices it should be SW(B2) SW(A2) SW(B1) SW(AI) SW(CO) 3- bit Adder-Subtractor circuit LEDI(C3)LED(S2) LED(SO) LEDI(SI)
Explanation / Answer
Copy the Verilog code below for your required case and run it in Quartus.
After verifying, go for simulation. There it will generate test bench and will give the waveform for each case.
module full_adder(
input a, //Input 1
input b, //Input 2
input cin, //Carry-in bit
output sum,
ouput cout //Carry-out bit
);
assign sum = ((~a & ~b) & cin) | ((a & ~b) & ( ~cin) | ((~a & b) & ~cin) | (( a & b) & cin);
aasign cout = (a & b) | (a& cin) | (b & cin);
endmodule
-__________________________________________________________________________-
// Full Adder using Half Adder
module half_adder( //module for half adder
input a,
input b,
output sum,
output cout //Carry-out bit
);
assign sum = (a & ~b) | (~a & b);
assign cout = A & b;
endmodule
module fa( //module for full adder
input a,
input b,
input cin, //Carry-in bit
output sum,
output cout //Carry-out bit
);
wire x, y, z;
half-adder U1(a, b, x, y); //Here, the output sum is x and carry out bit is y.
half-adder U2(x, cin, sum, z); //Here, the total sum is sum and caary out bit is z.
OR U3(y, z, cout);
endmodule
module OR( //module for OR operation
input a,
input b,
output c
)
assign c = a | b;
endmodule
____________________________________________________________________________
//3 bit adder subractor unit
module add_sub_unit( //main module for add subractor unit
input [2:0]a, //input 1 is of 3 bit
input [2:0]b, //input 2 is of 3 bit.
input cin_bin, //carry-in bit or borrow-int bit
input ctrl, //control signal for either add or subract
output cout_bout, //caary-out bit or borrow-out bit
output [2:0]result result is of 3 bit
);
wire c1, c2, c3;
wire [2:0] y; //Used for passing values of input numbers
reg m; //Register for storing control signal
always @(ctrl) begin
if (ctrl == 1) //for dterminig control signal for add or subtract
m = 1; //for subtraction
else
m = 0; //for addition
end
xor xor1(y[0], b[0], m); //XOR Operation Create the module for xor operation else you can directly use the xor gate in verilog.
xor xor2(y[1], b[1], m);
xor xor3(y[2], b[2], m);
bit1_add add [2:0] (a, b, {c2, c1, cin_bin}, {cout_bout, c2, c1}, result); //adding one bit at a time
endmodule
__________________________________________________________
I have provided the test bench for 3 bit add subtract unit below : -
//Test bench for adder subractor unit
module add_sub_unit;
reg [2:0]a;
reg [2:0]b;
reg cin_bin;
reg ctrl;
wire cout_bout;
wire [2:0] result;
add_sub_unit(.a(a),
.b(b),
.cin_bin(cin_bin),
.ctrl(ctrl),
.cout_bout(cout_bout),
.result(result) );
initila begin
#100;
a = 3'b010;
b = 3'b110;
cin_bin = 1;
ctrl = 0;
end
endmodule
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