Course: VHDL LISTING 7.3.1 Simple testbench for a half adder using projected wav
ID: 1715922 • Letter: C
Question
Course: VHDL
LISTING 7.3.1 Simple testbench for a half adder using projected waveforms library ieee; use ieee.std logic 1164.al1 testbench entity has no ports entity testbench is end testbench; S --tesS architecture waveform of testbench is -- Stimulus signals- to connect testbench to uuT input ports signal a tb, b tbstd logic _ Observed signals - to connect testbench to UUT output ports signal sum tb, carry out tbstd logic begin _ Unit Under Test port map UUT : entity half adder port map (a => a tb, b => b tb. sum => sum tb, carry out => carry out tb ); -- Signal assignment statements generating stimulus values a tbExplanation / Answer
signal ta, tb, tc, td, te: std_logic := '0';
begin
pa:process
begin
ta <= transport '1' after 3 ns;
ta <= transport 'Z' after 4 ns;
wait;
end process pa;
pb:process
begin
tb <= transport 'Z' after 4 ns;
tb <= transport '1' after 3 ns;
wait;
end process pb;
pc:process
begin
tc <= transport '1' after 3 ns, 'Z' after 4 ns;
wait;
end process pc;
pd:process
variable i: integer := 0;
begin
if (i = 0) then
td <= transport '1' after 3 ns;
i := i + 1;
else
td <= transport 'Z' after 4 ns;
wait;
end if;
end process pd;