Can someone please help me with these 1. A JK flip flop can be made to operate a
ID: 1845995 • Letter: C
Question
Can someone please help me with these
1. A JK flip flop can be made to operate as a D flip flop by adding an external Inverter gate and making the appropriate connections. Draw the schematic for this circuit.
2. A D flip flop can be made to operate in a toggle mode (divide its CLOCK input frequency by two) by making the appropriate connection (See Homework #3). Draw the schematic for this circuit.
3. Circuitry in a digital clock takes the output of a 65,536 Hz Oscillator and divides it down to 1 Hz (1 pulse per second). How many flip flops are needed to do this?
4. Write in the states (Reset, Set, Asynch. Reset, Asynch. Set) on the output waveform of the D flip-flop from Part 1.
5. Analyze the results recorded in Part 2, number 5. What is the relationship between the tco values? Why do ripple counters behave this way?
This is pt 2 number 5
Q0 Q1 Q2 Q3
tco = 7.469ns tco =9.201ns tco =10.715ns tco =13.411 ns
Explanation / Answer
1.a JK flip flop works as a D flip flop when you give D and D^ in the input.
so give input to the D input and inverse of input to the D^ by puting an inverter before D^2.
D^ represets inverse of D.
2. similarly Toggle mode DFF can be made if you just connect D and D^.
3. each flip flop will reduce the clk frequency by 2.
so to get approximately 65you need to heve 6 clk as 2^6 = 64 which is close to 65.536
4.the workings of DFF is it transfer the input when clk is high and when clk is low it shows its previous state.
5. in ripple counter each DFF output acts as a clock to the next DFF. so as if the output ripples through all the DFF.
it takes huge amount of delay. because input to output delay is the sum total of all DFF delay.
so period of input should be sufficiently larger then this.