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Part 1: Design the hardware and software driver that will implement a byte-wide

ID: 3548907 • Letter: P

Question

Part 1:

Design the hardware and software driver that will implement a byte-wide data transfer from your processor to a peripheral device. Each transfer must be accompanied by a strobe to deskew the data. Draw the UML sequence diagram and the timing diagram reflecting the operation of your design.

Part 2:

Design a model using a flow diagram or pseudo code, hardware, and the software driver that will implement a byte-wide bidirectional data transfer between your processor and four different peripheral devices utilizing a star bus configuration. Each leg of the star supports separate address and data bus components.   In addition to the address and data lines, identify all of the necessary control signals. Draw the timing diagram reflecting the operation of your design.

Design the hardware and software driver that will implement a byte-wide data transfer from your processor to a peripheral device. Each transfer must be accompanied by a strobe to deskew the data. Draw the UML sequence diagram and the timing diagram reflecting the operation of your design. Design a model using a flow diagram or pseudo code, hardware, and the software driver that will implement a byte-wide bidirectional data transfer between your processor and four different peripheral devices utilizing a star bus configuration. Each leg of the star supports separate address and data bus components. In addition to the address and data lines, identify all of the necessary control signals. Draw the timing diagram reflecting the operation of your design.

Explanation / Answer

part 1


Every peripheral device is controlled by writing and reading its registers. Most of the time a device has several registers, and they are accessed at consecutive addresses, either in the memory address space or in the I/O address space.

At the hardware level, there is no conceptual difference between memory regions and I/O regions: both of them are accessed by asserting electrical signals on the address bus and control bus (i.e., the read and write signals) and by reading from or writing to the data bus.

Not all computer plat form use a read and a write signal; some have different means to address external circuits. The difference is irrelevant at software level, however, and we'll assume all have read and write to simplify the discussion.

While some CPU manufacturers implement a single address space in their chips, some others decided that peripheral devices are different from memory and therefore deserve a separate address space. Some processors (most notably the   family) have separate read and write electrical lines for I/O ports, and special CPU instructions to access ports