Illegal Assignments -VHDL s1 Legal versus Illegal Assignments Below is a summary
ID: 2989778 • Letter: I
Question
Illegal Assignments -VHDL
s1
Legal versus Illegal Assignments Below is a summary of the most common mistakes made when assigning values to array type objects. In short, most mistakes fall in one (or more) of the causes listed below. A subsequent example illustrates the occurrence of such problems. Cause 1: Type mismatch (both sides of the assignment must be of the same type or of the same base type). Example: One side is BIT; the other is BOOLEAN. Cause 2: Size mismatch (both sides of the assignment must have the same number of bits or a predefined number of bits). Example: One side has 8 bits; the other has 4. Cause 3: Invalid value or invalid representation. Examples: BIT does not accept the value 'Z'; an integer cannot be represented with quotes; a bit vector requires double quotes. Cause 4: Incorrect indexing (the order and the range limits must be obeyed). Examples: The order (ascending or descending) of the index is reversed; the index values fall outside the actual range. Data Types 79 Cause 5: Incorrect assignment operator ("Explanation / Answer
a) s4(0)(0) <= s7(1,1,1);--illegal due to type mismatch;
b) s6(1) <= s4(1);--illegal due to type incorrect indexing;
c) s1 <= "00000000"--illegal due to type mismatch
d) s7(0)(0)(0) <= 'Z'--;...illegal due to invalid representation;
e) s2(7 DOWNTO 5) <= s1(2 DOWNTO 0);illegal due to type mismatch;
f ) s4(1) <= (OTHERS => 'Z');illegal due to invalid value
g) s6(1,1) <= s2;type and size mismatch;
h) s2 <= s3(1) AND s4(1);sitze and type mismatch;
i) s1(0 TO 1) <= (FALSE, FALSE);illegal due to type incorrect indexing;
j) s3(1) <= (3, 35, -8, 97);size mismatch;